Multiple triangle pixel-pipelines with span-range pixel interlock for processing separate non-overlapping triangles for superscalar 3d graphics engine

Abstract

A 3D graphics processor has parallel triangle pixel pipelines. One or more triangle setup engine(s) receives triangle primitives from a host or geometry engine and generates vertex color, texture and other attributes as well as their gradients. The triangle setup engine makes available all required triangle data to the triangle pixel pipelines. The triangle pixel pipelines accept the next triangle data on a demand basis, when finished with the previous triangle. Each triangle pixel pipeline has a span engine that generates endpoints along the 3 edges of the triangle where the horizontal lines (spans) intersect. Each triangle pixel pipeline also has a raster engine that receives the endpoints as well as gradients and generates color, texture and other attributes for each pixel along a span between endpoints. The raster engine then composites pixels from these attributes and updates visible pixels in the frame buffer. Pixel-memory coherency for Z-buffering is maintained by comparing an MSB part of the X pixel address and the span line number (Y address) of pixels being processed in each pipeline. Thus a span-range of pixels is compared rather than individual pixels. When span-ranges of pixels being rasterized in two different triangle pixel-pipelines overlap, one of the pipelines must stall until the other finishes the span-range. For rendering modes with alpha-blending enabled or Z-buffering disabled triangle input order must be maintained during pixel rasterization. To maintain proper order, bounding boxes of triangles processed in different pipelines are compared. When the bounding boxes overlap, even if the triangles do not overlap, one pipeline is held until the other completes the triangle.