The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2001

Filed:

Jul. 16, 1999
Applicant:
Inventors:

David B. Kieda, Salt Lake City, UT (US);

Michael H. Salamon, Salt Lake City, UT (US);

Assignee:

University of Utah Research Foundation, Salt Lake City, UT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H 1/126 ;
U.S. Cl.
CPC ...
H03H 1/126 ;
Abstract

Programmable analog delay line devices for analog signal processing are constructed on a single integrated circuit chip using a switched capacitor storage scheme for short-term storage of the voltage or charge waveform. These devices provide variable maximum delay times without signal attenuation and with delay-to-risetime ratios of up to 10,to 10,. A vector array of switched capacitor analog storage elements may be arranged in a ring-buffer topology, with the number of switched capacitor elements ranging from between about 10 and about 10,. Two internal counters incremented by a common clock keep track of the variable delay between an input signal and an output signal.


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