Controlled pmos load on a cmos pla

Abstract

A programmable logic array (PLA) AND plane receives data input signals from input registers and generates corresponding minterms. The minterms are OR-ed together to form a sum of products, which are provided to output latches and clocked out before the end of each clock cycle by an internal self-timed signal as PLA output data. The OR plane (or the AND plane, or both) includes NOR gates that include a plurality of NMOS transistors. Each NMOS transistor in a gate has its drain connected to a common NOR gate output node, its source connected to ground and its gate connected to receive a corresponding minterm from the AND plane. The NOR gate further includes a PMOS load transistor having its source connected to a voltage supply, its drain connected to the NOR gate output node and its gate connected to receive a timing signal that turns on the PMOS load transistor as the minterms are generated at the output of the AND plane and turns off the PMOS load transistor when the sum of products are provided at the output latches.