The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2001

Filed:

Dec. 19, 1997
Applicant:
Inventor:

Naoyuki Shigyo, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/9788 ;
U.S. Cl.
CPC ...
H01L 2/9788 ;
Abstract

A nonvolatile semiconductor memory has memory cells (,) each having an insulated-gate FET that has an information storage part. A semiconductor region (,) is formed at the surface of a channel region of each memory cell. The semiconductor region has the same conductivity type as a channel conductivity type and functions to decrease the strength of an electric field at the surface of the channel region. If the insulated-gate FET is of an n-channel type, the semiconductor region is of an n-type. The semiconductor region suppresses threshold voltage variations among the insulated-gate FETs of the memory cells and prevents soft-writing in the memory cells.


Find Patent Forward Citations

Shigyo, Naoyuki. (2001). Erasable and programmable nonvolatile semiconductor memory, semiconductor integrated circuit device having the semiconductor memory and method of manufacturing the semiconductor memory (U.S. Patent No. 6222224). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6222224

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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