Method of manufacturing a flash memory device

Abstract

There is disclosed a method of manufacturing a flash memory cell comprising the steps of forming a first ploysilicon layer pattern then forms a cell source; patterning a second polysilicon layer so that a gate electrode can be formed while the portion of the first polysilicon pattern where the cell drain will be formed is opened; forming a transistor at peripheral circuit area by performing ion injection process and a thermal process; forming a floating gate and a control gate by performing a self aligned etching process; and forming a cell source line and a cell drain by injecting cell source/drain ions. The flash memory cell formed thus has an increased coupling ratio since the control gate is formed to surround the floating gate, and also has an improved hot carrier reliability characteristic both at the peripheral circuit and the cell area upon operation of the device since the cell drain is formed after the thermal process for forming the peripheral circuit source and drain.