The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2001
Filed:
Sep. 09, 1998
Applicant:
Inventor:
Emery Sugasawara, Pleasanton, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/166 ;
U.S. Cl.
CPC ...
H01L 2/166 ;
Abstract
An on-chip misalignment indicator for measuring misalignment between layers of an integrated circuit die employs a first contact, and a second contact. A current path between the first and second contacts having a resistance that varies as a function of misalignment between successive layers of the integrated circuit die. Similarly, a method for detecting misalignment between layers of an integrated circuit die involves passing and measuring a current between a first contact. The amount of the current being indicative of an amount of misalignment between layers of the integrated circuit die.