Content addressable memory system with self-timed signals and cascaded memories for propagating hit signals

Abstract

A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits which are connected to a commonly shared bus. Each CAM array provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. Hit, match address and multiple match signals are provided from the CAM arrays to the logic circuits which are associated with the CAM arrays. The hit signals provided from the CAM arrays are propagated from upstream to downstream logic circuits in response to a self-timed signal which is delayed in time from the clock signal. The logic circuits prevent more than one match address signal provided from the CAM array from being transferred simultaneously to the commonly shared bus. The multiple match signals provided from the CAM arrays are propagated from upstream to downstream logic circuits. By observing the propagated hit and multiple match signals provided from the furthest downstream logic circuit and the match address signal on the commonly shared bus, a hit result of the system in a search operation is provided.