Data processing system having a synchronous memory with an output circuit which selectively outputs groups of m data bits

Abstract

A synchronous memory (,), comprising a row address circuit (,) latches a row address signal in response to a system clock signal and a binary select signal. The row address circuit produces at least one row select signal. A column address circuit (,) latches an initial column address signal in response to the system clock signal and the binary select signal. The column address circuit produces a plurality of column select signals in synchronization with the system clock signal. A memory array (,) is arranged in rows and columns of memory cells. Each memory cell stores a respective data bit. The memory array simultaneously produces an integral multiple of M data bits in response to the row select signal and the plurality of column select signals. An output circuit (OMUX) is coupled to receive the system clock signal and the integral multiple of M data bits. The output circuit produces a first data bit from a first group of M data bits on a bus (,) having M leads at a first time and a second data bit from a second group of M data bits on the bus having M leads at a second time after the first time in response to the system clock signal.