Pulse position modulation based transceiver architecture with fast acquisition slot-locked-loop

Abstract

A transceiver has a pulse position modulation (PPM) encoder, automatic gain control (AGC) circuit and timing recovery circuit. The PPM encoder illustratively has a frequency divider, slot selector, and mixer. The frequency divider divides the frequency of a clock signal to which the data of the non-return to zero (NRZ) signal are aligned to produce a half frequency clock signal. The slot selector selects pulses of the clock signal and the half frequency clock signal depending on logic values of the NRZ signal and a control signal to produce first and second slot selected signals. The mixer mixes the first and second slot selected signals to produce a PPM signal of the NRZ signal. The AGC circuit illustratively has a variable gain amplifier, a hysteresis comparator, an event detector, a timer, and a counter. The variable gain amplifier amplifies the PPM signal using a dynamically adjusted gain that depends on an inputted digital control value. The counter increments the inputted digital control value according to a clock signal outputted from the timer to increase the gain. The hysteresis comparator detects a signal level of the amplified PPM signal. The event detector causes the counter to decrease the inputted digital control value if the signal level is outside of a predetermined signal level range. The timing recovery circuit has a frequency track, a slot locked loop and a phase locked loop. The frequency track generates a coarse clock fx having a frequency that depends on a frequency of the PPM signal. The slot locked loop generates a resampling clock signal having a frequency that depends on the course clock fx and having slots locked to slots of the PPM signal. The phase locked loop locks a phase of the coarse clock fx to a phase of the PPM signal.