Semiconductor memory having reduced time for writing defective information

Abstract

The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information. The semiconductor memory of the present invention comprises a memory cell array,comprising (n+1) (n is a positive integer) word lines, a register unit,holding an encoded defect address for specifying a defective word line, a defect address decoder,for decoding the defect address from the register unit,to specify the defective word line, selection means S,˜Sn for selecting, for the i-th (1≦i≦n) output signal line of a row decoder,, one of the i-th and i+1-th word lines and connecting the selected word line to the i-th output signal line, and control means C,˜Cn each controlling corresponding one of the selection means S,˜Sn on the basis of an output of the defect address decoder,so as to select, for the output signal line of the row decoder,, one of the word lines except the defective word line in accordance with the arrangement order.