The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2001

Filed:

Nov. 29, 1999
Applicant:
Inventor:

Koji Naganawa, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/134 ;
U.S. Cl.
CPC ...
G11C 1/134 ;
Abstract

A nonvolatile semiconductor memory device includes nonvolatile memory cells, redundant memory cells, a circuit for performing a write and erase in and from the nonvolatile memory cells, an erase verify circuit, a count circuit, a comparison circuit, and a control circuit. The redundant memory cells are switchable from the nonvolatile memory cells. The erase verify circuit sequentially verifies erase of the nonvolatile memory cells one by one. The count circuit counts memory cells not erased to a predetermined state. The comparison circuit compares the count value of the count circuit with a set value set based on the number of redundant memory cells. The control circuit controls the respective functions of the erase verify circuit, count circuit, and comparison circuit on the basis of the comparison result of the comparison circuit. The control circuit controls the respective functions of the erase verify circuit, count circuit, and comparison circuit so as to execute verify for memory cells to be verified next until the count value exceeds the set value. An erase verify method is also disclosed.


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