The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2001
Filed:
May. 17, 1999
Craig S. Lytle, Mountain View, CA (US);
Donald F. Faria, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device integrated circuit incorporating a first-in, first-out memory block (,). First-in, first-out memory block (,) is coupled to a programmable interconnect array (,). Signals from the logic array blocks (LABs) (,) are connected to the control inputs of the first-in, first-out memory (,). In one embodiment, the programmable interconnect array (,) may be programmably coupled to the control inputs (,) of the first-in, first-out memory block. Status flag signals (,) from the first-in, first-out memory block (,) are programmably coupled to the programmable interconnect array (,). Data input (,) and data output (,) to first-in, first-out memory block (,) may be coupled to external, off-chip circuitry.