Method and apparatus for a multiple stage sequential synchronous regulator

Abstract

A multiple stage sequential synchronous regulator including multiple switch stages activated in a sequential manner to reduce the frequency, stress and power loss per stage. In the preferred embodiment, each stage is implemented using buck regulator topology including an inductor and two synchronous switches, preferably comprising MOSFETs. A sequential logic circuit asserts corresponding enable signals to activate each of the stages one at a time in sequential manner. Each stage also receives a pulse width modulated (PWM) signal for activating the first synchronous switch during a power phase and then activating the second synchronous switch during a flux reversal phase for the enabled stage. The time sharing of multiple stages reduces the average current per stage and allows increased utilization of the switching parts per stage. Thus, the typically large and expensive power inductors and switches are replaced with significantly smaller, lighter and cheaper components. Furthermore, each switched device can be pushed past its rated limits due to smaller average current, thereby increasing the efficiency of each of the parts. A single output capacitor is coupled to all of the stages for filtering the output voltage. The output capacitor can remain small since it sees the cumulative frequency of all of the switch stages combined.