The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2001

Filed:

Feb. 01, 2000
Applicant:
Inventors:

Shinji Koga, Tokyo, JP;

Kazuhiro Morishita, Fkuoka, JP;

Katsumi Satoh, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/974 ; H01L 3/1111 ;
U.S. Cl.
CPC ...
H01L 2/974 ; H01L 3/1111 ;
Abstract

The present invention relates to a diode, and has an object to simultaneously implement a high di/dt capability, a low reverse recovery loss and a low forward voltage and to suppress generation of voltage oscillation. In order to achieve the above-mentioned object, life time killers are selectively introduced into a semiconductor substrate (,) comprising a P layer (,), an N,layer (,) and an N,layer (,). A density of the introduced life time killers is the highest in a first region (,) adjacent to the P layer (,), and is the second highest in a second region (,) in the N,layer (,). The life time killers are not introduced into a third region (,). Accordingly, a life time in the N,layer (,) is expressed by the first region (,)<the second region (,)<the third region (,). The second region (,) and the third region (,) are adjacent to the P layer (,). In addition, the second region (,) annularly surrounds the third region (,).


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