The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2001
Filed:
Jul. 28, 1999
Anne-Marie Dutron, Le Coudray Montceaux, FR;
Patrick Raffin, Joinville le Pont, FR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The method of the present invention is directed to the formation of an arsenic silicon glass (ASG) film onto a silicon structure and finds a valuable application in the buried plate region formation process in the manufacture of deep trench cell capacitors in EDO and SDRAM memory chips. The starting structure is state-of-the-art and consists of a silicon substrate coated by a patterned SiO2/Si3N4 pad layer which defines deep trenches formed therein by etching. At the beginning of the conventional buried plate region formation, the interior side walls of deep trenches are coated with an arsenic doped silicon glass (ASG) film resulting from the co-pyrolysis of TEOS and TEASAT in a vertical hot dual wall LPCVD reactor as standard. According to the present invention, a flow of O2 is added which makes this co-pyrolysis of TEOS and TEASAT no longer interactive. As a consequence, the improved process is much better controlled than the conventional one. The ASG film is conformally deposited onto the structure with a high degree of thickness and arsenic concentration uniformity within a same wafer and from wafer to wafer of the lot.