Process for fabricating a semiconductor non-volatile memory device with shallow trench isolation (sti)

Abstract

Process for fabricating a semiconductor non-volatile memory device arranged in rows and columns in a matrix structure, including a first step of forming active area's parallel lines delimited by field oxide lines using a Shallow Trench Isolation process, a second step of forming matrix rows which extend transversally to the active area lines, a third step of forming common source lines alternated between pairs of the matrix rows. The second step includes a first sub-step of forming first lines in a first polysilicon layer, along the active area lines, a second sub-step of forming an intermediate dielectric layer, a third sub-step of forming second lines in a second polysilicon layer for defining the matrix rows, a fourth sub-step of defining the intermediate dielectric layer, a fifth sub-step of etching the first polysilicon lines. The first polysilicon lines have interruptions in regions of the active area lines corresponding to the future common source lines of the matrix, so that, during the fifth etching sub-step, simultaneously with the first polysilicon lines etching, the regions of the active area lines not covered with the first polysilicon lines are etched in order to reduce the difference of level along the common source lines between the regions of the active area lines and the regions of the field oxide lines and consequently to guarantee the electrical continuity of the common source regions of the memory device.