The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2001
Filed:
May. 20, 1998
Sony Corporation, Tokyo, JP;
Abstract
The layout of a semiconductor IC is determined making use of a first logical cell of an ordinary flip-flop based on a logical net. Logical simulation is performed according to the result of the layout, that is, the layout information. The possibility of erroneous operation caused by timing deviations is verified by comparing the timing information from the result of the logical simulation with the design specifications. Furthermore, the logical cells at points where there is the possibility of erroneous operation caused by timing deviations are replaced by second or third logical cells having delay elements connected to data input or output terminals of the flip-flops. The final layout of the semiconductor IC is then decided.