Processing unit for a computer and a computer system incorporating such a processing unit

Abstract

A computer system has a plurality of processing units (,-,-,-n) connected via one or more system buses (,-,-,). Each processing unit (,-,-,-n) has three or more processors (,-,-,-,) on a common support board (PL) and controlled by a common clock unit (,). The three processors (,-,-,-,) perform the same operation and a fault in a processor (,-,-,-,) is detected by comparison of the operations of the three processors (,-,-,-,). If one processor (,-,-,-,) fails, the operation can continue in the other two processors (,-,-,-,) of the processing unit (,-,-,-n), at least temporarily, before replacement of the entire processing unit (,-,-,-n). Furthermore, the processing unit (,-,-,-n) may have a plurality of clocks (A,B) within the clock unit (,), with a switching arrangement so that the processors (,-,-,-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (,) may be connected in common to the processors (,-,-,-,), so that failure of one cache memory (,) permits the processing unit (,-,-,-n) to continue to operate using the other cache memory (,). Coherence of the contents of the cache memories (,) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (,-,-,-,) of a processor (,-,-,-,) which differs from that in the external cache memory (,). Coherence of protocols may also ensure that data in caches (,) of the different processor units (,-,-,-n) are always correct.