Data processing system and method capable of halting supply of clock signal without delay

Abstract

A data processing system which executes pipeline processing that decodes a subsequent instruction in an execute phase of a current instruction in response to a clock signal. The data processing system includes a CPU and a mode management block. The CPU supplies an address bus with at least one predetermined address in an execute phase of a clock supply stop instruction. The mode management block produces a clock stop signal if the predetermined address agrees with a self-address assigned to the management block in advance, thereby halting the supply of the clock signal. This makes it possible to solve a problem of a conventional data processing system in that it executes the instruction next to the clock supply stop instruction in spite of execution of the clock supply stop instruction because the clock stop signal is actually output when the clock supply stop instruction shifts from the execute phase to the write back phase, in which case the next instruction proceeds in the execute phase.