Methods of controlling memory buffers having tri-port cache arrays therein

Abstract

Methods of controlling memory buffers having tri-port cache arrays therein include the steps of reading data from a current read register in the cache memory array to an external peripheral device, and writing data from an external peripheral device to a current write register in the cache memory array. Tri-port controller logic and steering circuitry are also preferably provided for performing efficient read and write arbitration operations to make next-to-read and next-to-write registers always available in the cache memory array. The use of four separate registers in the cache memory array, efficient steering circuitry and the tri-port controller logic essentially eliminates the possibility that gaps or stoppages will occur in the flow of data into and out of the buffer memory device during read and write operations. To always maintain a source of available data for reading or available space for writing, even under worst case operating conditions including burst mode operation, the step of performing write arbitration comprises determining a next-to-write register as a first free register in the cache memory array if the current read and write registers are different registers and the step of performing read arbitration comprises determining a next-to-read register as the current write register if the current write register contains next-to-read data relative to data in the current read register. The step of performing read arbitration may also comprise determining the next-to-read register as a second free register in the cache memory array if the current read and write registers are different registers and the next-to-read register is not the current write register, or as the next-to-write register if the current read and write registers are the same register.