Error master detector

Abstract

An error master detector for use in a system having at least two bus masters which request bus use and a bus arbitrator for receiving the bus use requests of the bus masters to arbitrate the bus use. The error master detector includes a bus grant signal synchronizer for latching a bus grant signal generated from the bus arbitrator by a predetermined bus clock; a latch clock generator for latching a latch clock for combining the bus grant signal generated from the bus arbitrator and an output signal synchronized in the bus grant signal synchronizer to latch the bus master information receiving the bus grant signal; a first latch unit for latching an output signal of the bus grant signal synchronizer in synchronous with the latch clock, and clearing the latched value when the bus cycle is normally finished; a second latch unit for latching an output signal of the first latch unit in synchronous with the latch clock; a master information selector for generating the output signal of the first latch unit when the second latch unit has no latched bus master information, and generating the output signal of the second latch unit when the second latch unit has latched master information; and an error master storage unit for storing data selected from the master information selector when a bus cycle error occurs. This way when an error occurs in a bus system in which the arbitration cycle and the data transfer cycle are separately performed, the bus master which causes the error can be easily detected so that the system can be rapidly repaired.