Method and apparatus for sequential memory addressing

Abstract

Circuits for sequentially addressing memory locations in time with pulses received from a clock are disclosed. The circuits may provide a positive voltage output signal at successive output nodes associated with corresponding stages in the circuit responsive to the application of a clock signal to the circuit stages. The circuit may comprise at least first and second stages wherein said first stage comprises means for providing a positive voltage signal at a first output node in the first stage in response to application of a first positive clock pulse to the first stage, and wherein said second stage comprises means for providing a positive voltage signal at a second output node in the second stage in response to application of a second positive clock pulse to the second stage. Addressing of memory locations that contain pixel information for a video display is one particular application in which sequential addressing may be required. Sequential addressing is useful in video applications because it permits sequential selection of the pixel rows and columns that make up the display screen. Sequential scanning of the memory locations for screen information can be carried out in conjunction with the scanning of an electron source across the screen of the display.