The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2001
Filed:
Aug. 04, 1997
Kelvin McCollough, Austin, TX (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
A dual bandwidth PLL based clock generation circuit that enables device execution after frequency/phase lock has been safely achieved is provided. A PLL (,) generates a PLL clock output to a divider (,), which divides the PLL clock at a system clock output. A frequency detector (,) detects frequency/phase lock of the PLL and outputs a bandwidth control signal to selectively operate the PLL (,) in a wide or narrow bandwidth mode until the system clock is stabilized to within a predefined bandwidth of a target frequency while the PLL (,) is operating in the narrow bandwidth mode. The frequency detector (,) outputs a frequency lock signal that enables execution in a CPU (,) upon detecting that the PLL (,) has safely locked to a desired output frequency. Thus, the present invention provides a stable system clock for the system prior to the CPU (,) being allowed to begin its operation, thereby substantially avoiding system failures that may result from frequency overshoot of the system clock.