The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2001
Filed:
Jun. 11, 1999
Jeffrey E. Koelling, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An architecture for a high-capacity high-speed synchronous dynamic random access memory (SRAM) (,) is disclosed. The SDRAM (,) includes memory cells logically arranged into a number of array banks (,). The array banks (,) each include first sub-banks (,) situated toward a first end of the SDRAM and second sub-banks (,) situated toward a second, opposing end of the SDRAM (,). Sub-bank buses (,), each of which includes a number of data I/O lines, couple each of the first sub-banks (,) to a first I/O circuit (,) situated toward the first end of the device, and couple each of the second sub-banks (,) to a second I/O circuit (,) situated toward the second end of the device. In this manner, overlap of the sub-bank buses (,) is limited toward the first and second ends of the device, eliminating the need to run data I/O lines across the device, and thus preventing a data I/O line routing bottleneck in the central portion of the SDRAM (,).