The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2001

Filed:

Dec. 22, 1998
Applicant:
Inventors:

Chingchi Yao, Saratoga, CA (US);

Chung-Jen Chien, Saratoga, CA (US);

Assignee:

OKI Semiconductor, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/600 ;
U.S. Cl.
CPC ...
G11C 1/600 ;
Abstract

A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.


Find Patent Forward Citations

Yao, Chingchi. (2001). Nonvolatile memory cell structure for integration with semiconductor logic devices and method of using same (U.S. Patent No. 6215701). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6215701

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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