Architecture, circuitry and method for configuring volatile and/or non-volatile memory for programmable logic applications

Abstract

Architecture, circuitry, and methods are provided for operating a high speed, volatile programmable logic integrated circuit using back-up non-volatile memory cells configured on an integrated circuit separate from the programmable logic integrated circuit. The lower density non-volatile memory cells can be formed on an integrated circuit using fabrication steps similar to those used to form, e.g., EEPROM devices or, more specifically, flash EEPROM devices. The programmable logic integrated circuit includes high density, volatile memory cells integrated with high speed, low density configurable CMOS-based logic. By using two separate processing technologies on two separate and distinct monolithic substrates, and interconnecting the separate integrated circuits on a singular monolithic substrate, the advantages of non-volatility can be combined with a high speed programmable circuit. The pins extending from the programmable logic device can be mounted in various ways to corresponding receptors on a printed circuit board. The present architecture, circuitry, and method thereby presents a packaged device which inherently has the same characteristics as a single integrated circuit, yet is actually two integrated circuits having the benefits of non-volatility as well as the benefits of higher speed, higher density volatile logic blocks within a programmable logic device or complex programmable logic device.