Embedded memory logic device using self-aligned silicide and manufacturing method therefor

Abstract

The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.