The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2001

Filed:

May. 14, 1999
Applicant:
Inventor:

Koji Torii, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B24B 4/900 ;
U.S. Cl.
CPC ...
B24B 4/900 ;
Abstract

A semiconductor wafer polishing device is capable of improving controllability of a residual layer thickness and improving a production ability. The semiconductor wafer polishing device performs polishing of an interlayer insulation layer on a semiconductor wafer by performing divided polishing for the interlayer insulation layer by means of a platen, measuring a layer thickness of the interlayer insulation layer during a polishing process by the platen, and performing final polishing depending upon a result of measurement.


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Torii, Koji. (2001). Semiconductor wafer polishing device and polishing method thereof (U.S. Patent No. 6213847). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6213847

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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