The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2001

Filed:

Jul. 22, 1997
Applicant:
Inventors:

Hui-Ling Lou, Murray Hill, NJ (US);

Carl-Erik Wilhelm Sundberg, Chatham, NJ (US);

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/100 ;
U.S. Cl.
CPC ...
G06F 1/100 ;
Abstract

Digital data is stored in an analog memory device using coded modulation techniques. The memory device includes a number of memory cells, each capable of storing one of a number of different levels. A given set of b information bits to be stored in the memory device is first coded in a convolutional or block coder to generate a set of coded bits which includes more than b bits. The set of coded bits is then mapped to one or more corresponding levels, and the one or more levels are each stored in a separate cell of the memory device. In a one-dimensional embodiment, the coding may involve applying a rate 1/2 convolutional code to i least significant bits, i=1, 2, . . . , and mapping the resulting b+i coded bits to one of 2,distinct levels in a one-dimensional AM signal set. In embodiments of the invention which utilize multidimensional signal sets, a given set of bits is mapped to a signal in an m-dimensional signal set, with or without coding of the bits, and each of the m dimensions of the selected signal is then stored as a level in a separate cell of the analog memory device. The invention increases the storage capacity of the memory device for a given readout error probability, or alternatively improves the error probability for a given storage capacity. Readout performance may be further improved by using a multiple read-and-sum unit to generate a readout value for a given stored level based on a sum or average of several different readouts of the stored level.


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