Automatic adjustment for counting instrumentation

Abstract

A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation. Thereafter, an instrumentation logic block associated with the instrumentation entity is automatically generated and utilized for counting occurrences of the count event detected by the instrumentation entity. Finally, the design cycle is encoded within the instrumentation entity, such that the output logic block is automatically adjusted to count in conformity with the design cycle.