Fast response automatic gain control

Abstract

A two-step automatic-gain-control (AGC) loop for use with a receiver. An AGC amplifier amplifies a received signal. From an output signal from the AGC amplifier, a received-signal-strength-indicator (RSSI) circuit generates an RSSI signal proportional to a received-signal-power level of the received signal. An RSSI-mapping circuit has an RSSI-mapping table. From the RSSI signal, the RSSI-mapping circuit, using the RSSI-mapping table, generates an AGC signal. An AGC-storing circuit stores the AGC signal. The AGC amplifier uses the stored-AGC signal to adjust the AGC gain. A converter circuit converts the output signal from the AGC amplifier to an in-phase component and a quadrature-phase component at a processing frequency. The error circuit determines an error signal from the in-phase component and the quadrature-phase component. When the error signal indicates the in-phase component and the quadrature-phase component are high, the integrate-and-dump circuit increments a counter of the integrate-and-dump circuit. When the error signal indicates the in-phase component and the quadrature-phase component are low, the integrate-and-dump circuit decrements the counter of the integrate-and-dump circuit. An AGC-convergence-rate multiplier normalizes an output of the integrate-and-dump circuit, thereby generating a normalized signal. The AGC-storing circuit updates the AGC signal from the normalized signal. From the updated AGC signal, the AGC circuit adjusts the AGC gain.