The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2001

Filed:

Dec. 14, 1998
Applicant:
Inventor:

Mamoru Fujita, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor memory includes a plurality of memory cell arrays each composed of a plurality of memory cells, each of the memory cell arrays including a plurality of main word lines, each of which is composed of a pair of sub-word lines each connected to a plurality of memory cells, means for driving the main word lines, power supply voltage supply line driving means connected to the sub-line lines. When a redundant word line used in place of a specific sub-word line including a defective sense amplifier is activated, the number of the sub-word lines activated when a data input/output is conducted is different from the number of sub-word lines activated in a refreshing operation. When the data input/output is conducted, a replacement of a sub-word line is executed on the basis of the result of a comparison between an externally supplied row address and an internally stored row address. When the refreshing operation is conducted, the replacement of the sub-word line is executed on the basis of an output of an internal refresh address counter and simultaneously with an ordinary refreshing operation.


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