Multiplexer with short propagation delay and low power consumption

Abstract

A digital multiplexer with low power consumption and a data to output propagation delay of about one gate includes a plurality of pairs of emitter coupled input transistors. The emitters of each pair of input transistors are connected to the collector of a corresponding selection transistor. The emitters of the selection transistors are connected to a main current source. The data at a selected pair of complimentary data inputs is transmitted to complimentary outputs by activating the selection transistor connected to the pair of input transistors corresponding with the selected inputs, thereby connecting the current source in series with those input transistors. The power consumption of the multiplexer is low because the single main current source is used for all of the inputs. Cascode transistors are connected between the collectors of the input transistors and the bases of output transistors. The cascode transistors isolate the bases of the output transistors from the relatively large capacitance associated with the collectors of the input transistors, enabling the output transistors to switch more quickly, which reduces the data to output propagation delay. Additionally, bleed current sources are connected to the emitters of the cascode transistors. The bleed currents keep the cascode transistors always “on” in a conducting state, which enables the cascode transistors to switch more quickly, thereby reducing the data to output propagation delay. Accordingly, the multiplexer has low power consumption and a short data to output propagation delay.