The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2001

Filed:

Jun. 13, 2000
Applicant:
Inventor:

Stepan Iliasevitch, Nepean, CA;

Assignee:

Nortel Networks, Limited, Montreal, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 3/16 ;
U.S. Cl.
CPC ...
G05F 3/16 ;
Abstract

A signal voltage converter converts a 0V to −5V input signal to a +5V to 0V output signal using PMOS transistors for both pull-up and pull-down of the output. Bipolar transistor level shifters and PMOS current mirrors are used to control the pull-up and pull-down transistors in conjunction with a clamp circuit. Output signal transitions are matched for both transition directions to reduce signal timing distortion, and this can be further enhanced by an optional circuit for supplying a controlled current for the clamp circuit.


Find Patent Forward Citations

Iliasevitch, Stepan. (2001). Mos transistor output circuits using pmos transistors (U.S. Patent No. 6211660). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6211660

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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