Constant reconstruction processor that supports reductions in code size and processing time

Abstract

A processor for executing operations based on instructions includes an operation constant register,, a branching constant register,, a decoding unit,for decoding an instruction stored in an instruction register,, a constant register control unit,, and an execution unit,. When the decoding unit,finds that the instruction includes a constant to be stored in the branching constant register,, the constant register control unit,shifts a present value in the branching constant register,and inserts the constant to be stored, thereby storing a new constant in the branching constant register,. When the decoding unit,finds that a constant is to be stored in the operation constant register,, the constant register control unit,shifts the present value in the operation constant register,and inserts the constant to be stored, thereby storing a new constant in the operation constant register,. When the decoding unit,finds that the instruction includes a branch operation, the execution unit,executes the branch operation using the constant stored in the branching constant register,. When the decoding unit,finds that the instruction includes an arithmetic operation, the execution unit,executes the arithmetic operation using the constant stored in the operation constant register