The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2001
Filed:
Aug. 12, 1999
Brian L. Brown, Sugar Land, TX (US);
David R. Brown, Sugar Land, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A semiconductor memory (,) device having a redundancy test scheme is disclosed. A memory cell array (,) includes a normal section (,) and a redundant section (,and,) of memory cells. In a normal mode of operation, the redundant section is selected if an applied address (ADD) corresponds to a defective bit in the normal section. In a redundant test mode of operation, the redundant section is selected based on a redundant test address (DFTRA, DFTCA). If the redundant test address is in the normal select logic level, a normal decode section (,and,) is selected. The redundant test address and a redundant test activation signal are applied to a redundant decoder (,). If the redundant test address is in a redundant select logic level and the redundant test activation signal is active, the redundant decoder is selectable based on the applied address value.