Semiconductor memory device which continuously performs read/write operations with short access time

Abstract

A semiconductor memory device such as a DRAM device in which, in each write or read cycle, a plurality bits of data are written to or read from memory cells as a burst. The semiconductor memory device includes: a plurality of write/read circuits for reading data from selected memory cells to data lines and writing data from the data lines to selected memory cells; a column selector for distributing data from an input/output line to the data lines, and outputting data from the data lines to the input/output line; and a plurality of data latches inserted into data line circuit portions between the column selector and the write/read circuits, for temporarily storing data to be written to or read from the memory cells as a burst. In a write cycle, after data stored in the latches is written into memory cells and after elapsing a predetermined time period required for a precharge operation of the bit lines, the next write cycle is started. In a read cycle, after data is read out from memory cells into the data latches and after performing a precharge operation of the bit lines, the next read cycle is started.