Translation lookaside buffer (tlb) including fast hit signal generation circuitry

Abstract

A memory unit is presented including a data array for storing data items (e.g., instructions and/or data) a hit circuit, and a miss circuit. The data items stored within the data array are accessed by multiple data access signals, wherein assertion of one of the data access signals indicates the presence of a requested data item within the data array. The hit circuit includes multiple driver cells coupled to two signal lines: a bit line and a bit′ line. Each driver cell receives a different one of the data access signals. When one of the data access signals is asserted, the receiving driver cell drives the bit line toward a first voltage level (e.g., V,), and drives the bit′ line toward a second voltage level (e.g., V,). The miss circuit is coupled to the bit and bit′ lines, and drives the bit line toward V,. The strength with which the miss circuit drives the bit line toward V,is less than the strength with which the hit circuit drives the bit line toward V,such that a differential voltage is quickly and reliably developed between the bit and bit′ lines which indicates the presence or absence of the requested data item within the data array. A translation lookaside buffer (TLB) implementation of the memory unit is described, as is a cache unit including the TLB implementation, a processor including the cache unit, and a computer system including the processor.