The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2001

Filed:

Apr. 19, 1999
Applicant:
Inventors:

Kouichi Kumagai, Tokyo, JP;

Susumu Kurosawa, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/920 ; H03K 1/9094 ;
U.S. Cl.
CPC ...
H03K 1/920 ; H03K 1/9094 ;
Abstract

In a semiconductor integrated circuit, a control transistor,and a potential clamp circuit,are arranged between a power supply line,and a virtual power supply line,. Even in a sleeve mode where the control transistor,is turned off, the potential clamp circuit,-,clamps the virtual power supply line,at a certain potential to hold a potential state (high level or low level) of each node of a logical circuit. At this time, each FET forming the logical circuit is applied with a back bias so that a threshold voltage Vt becomes higher than that in an active mode. Therefore, a leakage current can be decreased. In the semiconductor integrated circuit, the threshold voltage Vt of the control transistor,can be selected to be equal to that of one FET of the complementary FET forming the logical circuit. Therefore, the layout area and the number of manufacturing steps can be reduced.


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