The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2001

Filed:

Jun. 04, 1999
Applicant:
Inventor:

Yukio Yasuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/900 ; H01L 2/9866 ; H01L 2/9861 ; H01L 3/1107 ;
U.S. Cl.
CPC ...
H01L 2/900 ; H01L 2/9866 ; H01L 2/9861 ; H01L 3/1107 ;
Abstract

The present invention provides a power semiconductor device comprising a semiconductor substrate; a voltage-controlled transistor comprising a first electrode formed on the lower surface of the semiconductor substrate, a gate formed on the semiconductor substrate with a gate oxide interpolated in between and a second electrode formed on the semiconductor substrate; and a zener diode formed on the upper surface of the semiconductor substrate so as to be connected between the gate and the second electrode; wherein p-type regions and n-type regions alternately formed between the zener diode and the second electrode on the semiconductor substrate, a plurality of pad electrodes on the semiconductor substrate provided with the alternate p-type regions and n-type regions so as to allow one or not less than two diodes are series connected between the zener diode and the second electrode, and the distance between the adjacent pad electrodes is set so that when the diode is subjected to a current not less than a predetermined value, the respective pad electrodes are fused so that short-circuiting occurs between the adjacent pad electrodes.


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