Method for improving interrupt response time

Abstract

A method and apparatus for rapidly detecting the source of an interrupt. A multi-bit interrupt state register is provided which registers the occurrence of an interrupt in response to an interrupt event. The outputs of the interrupt state register are coupled to an interrupt vector register which is memory mapped and directly accessible to a processor via load and store instructions. The interrupt vector register is continuously updated to reflect the current state of the interrupt state register. The processor may read the interrupt vector register with low latency, store the contents of the interrupt vector register in a general purpose register within the processor, and determine the source of interrupts via bit test instructions performed on the general purpose register. The bits interrupt state register may be cleared by the processor by upon the issuance of a memory mapped write command to a clear register. Writing to the clear register generates clear pulses for selected bits that result in the clearing of the respective bits of the interrupt state register. Additionally, an interrupt status register is provided which the processor can read over a bus. The interrupt status register contains interrupt events which are accessible by the processor with a greater read access latency than the interrupt state register.