Method for distributing interrupts in a multi-processor system

Abstract

An interrupt messaging scheme for a multiprocessing computer system where a dedicated bus to carry interrupt messages within the multiprocessing system is eliminated. Instead, an interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. Various interrupt requests are transferred through a predetermined set of discrete interrupt message packets. Interrupt message initiators—an I/O interrupt controller or a local interrupt controller (in case of an inter-processor interrupt)—may be configured to generate appropriate interrupt message packets upon receiving an interrupt request. A suitable routing algorithm may be employed to route various interrupt messages within the system. Simultaneous transmission of interrupt messages from two or more interrupt controllers may be possible without any need for bus arbitration. Interrupt response is decoupled from corresponding interrupt message and the interrupt messaging protocol may be implemented independently of the physical properties of a system bus carrying interrupt packets. System flexibility in managing interrupts is thus improved.