Destructive read type memory circuit, restoring circuit for the same and sense amplifier

Abstract

A restoring circuit,provided for each of the memory blocks,and,having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder,The present row address is held in one of the registers. When amplification is started by a sense amplifier,transfer gates,and,connected between the bit lines BL,and *BL,and the sense amplifier,are turned off to decrease the load of the sense amplifier,the amplified signal is stored in a buffer memory cell circuit,and accessing is completed with omitting restoring to the memory cell,While the memory cell block,is not selected, the data held in the buffer memory cell circuit,is stored into the memory cell row addressed by the content of the selected register. The sense amplifier,has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.