Digital to analog convertor having a dc offset cancelling device and a method thereof

Abstract

A device and a method for canceling DC offset resulting from digital to analog conversion, wherein the device is coupled to a digital to analog comparator (i.e.—DAC), the device comprising of: an adder, coupled to the DAC, for adding a digital input signal IN(n) to a compensation signal CS(w−1), and sending the sum of IN(n) CS(w−1) to the DAC. An analog comparator, coupled to the DAC, for sampling the output signal OUT(t) of the DAC, for comparing the sampled signal ACS(n) to a first reference voltage VREF and for outputting a signal ACO(n) which represents the result of the comparison between ACS(n) and VREF. A DAC emulator, coupled to the DAC, for compensating for a time lapse between the appearance of a digital input signal IN(n) appearing at the input of the adder and an OUT(t), wherein OUT(t) resulted from IN(n). A digital comparator for receiving the output signals DES(n) of the DAC emulator, comparing DES(n) to a second reference value DREF and outputting a signal DCO(n) which represents the result of the comparison between DES(n) to DREF, and an offset calculation unit, coupled to the analog comparator and to the digital comparator for comparing ACO(n) and DCO(n) and sending to the adder, a compensation signal CS(n) which represents the result of the comparison between ACO(n) and DCO(n). The analog and digital comparator are driven by a clock signal which is not correlated to IN(n).