Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units

Abstract

Apparatus for clock signals distribution with continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU. Switching is transparent to load circuits which utilize these clock signals, by continuously keeping the output clock signals in the CDU and the redundant CDU frequency and phase coherent, by generating each output clock signal from a reference signal, using an adaptive PLL circuitry at each CDU, and pre-adjusting the phase of each output clock signal of the redundant CDU to the corresponding output clock signal of the CDU. In the event of a failure in the CDU, the output is taken from the redundant CDU immediately after failure detection. The phase of the reference frequency output clock signal of the standby CDU module is adjusted to the phase of the active CDU module by adding or subtracting an input signal to the phase error signal, which is generated in a PLL circuitry of the redundant CDU module. An adjustable delay line is used at each CDU to delay the clock signal that is provided from the active into the redundant CDU. The delay time is adjusted to obtain phase coherence between the high frequency outputs of the two CDUs and a fine adjustment on the reference frequency output clock signal. The redundant CDU module becomes active and connected to the load, whenever a failure is detected in the active CDU module.