Unlimited phase tracking delay locked loop

Abstract

The invention comprises a phase shifter reset circuit, for phase shifting an input signal, and includes a phase shifter, for shifting the phase of an input signal by a phase determined by a phase shift reference signal and a resetter, for resetting the phase shift reference signal in response to a trigger signal. Also included is a fixed phase shifter for shifting the phase of the input signal by a predetermined phase shift which is connected in parallel with said phase shifter and a threshold detector circuit set to a threshold level which is substantially equivalent to the voltage level required by the phases shifter to produce the same phase shift as is introduced into the input signal by the fixed phase shifter. A bypass circuit is disposed between the phase shifters and the output and includes a switch for selecting a signal from either the phase shifted input signal or said fixed phase shifted signal. The bypass circuit responds to a switching signal in order to switch from the phase shifted input signal to said fixed phase shifted signal for a predetermined period of time, during which time the trigger signal for resetting the phase shifter is generated, before switching back to the phase shifted input signal. The invention includes a method of resetting a phase shifter. Also included in the invention is a delay locked loop incorporating the phase shifter reset circuit and a method of inserting a delay into an input signal using a delay locked loop according to the invention.