Power on reset circuit with power noise immunity

Abstract

A power on reset includes a latch controller and a latch circuit. The latch controller sets the latch circuit to an initialization state when a power supply voltage is less than a first threshold voltage during power-up, so that a power on reset signal from the latch circuit has the power supply voltage, a logical high level (i.e., goes to a logically activated state). The latch controller resets the latch circuit when the power supply voltage becomes higher than a second threshold voltage which is higher than the first threshold voltage, so that the power on reset signal goes to the ground voltage Vss, a logical low level (i.e., goes to a logically inactivated state). According to such a circuit configuration, even though the power supply voltage oscillates around a voltage at a point in time when the power on reset signal transitions from the power supply voltage to the ground voltage, the power on reset signal continues to be maintained at a previous set state. This prevents logic elements, to be set at a desired state during power-up, from performing needless operations because of the power oscillation. Therefore, the power on reset circuit according to the present invention has an improved power noise immunity.