Flash-type nonvolatile semiconductor memory devices for preventing overerasure

Abstract

A nonvolatile semiconductor memory device includes a p-type semiconductor substrate having a surface region, and bit lines formed as n-type first diffusion regions in the surface region, extending in a column direction. The bit lines define between them a plurality of separated, parallel channel regions, extending in a row direction. A plurality of conductive floating gates are formed over first portions of respective channel regions on a first insulating layer, and extend over portions of the first diffusion regions. A plurality of conductive control gates is formed to extend over the floating gates, and over second portions of the channel regions that are not covered by the floating gates. The control gates are separated from the floating gates and from the second portions by additional insulating layers. A common source line is formed by an elongated conductor extending in the column direction, over the control gates and insulated from them. A plurality of n-type second diffusion layers are formed in the surface region between successive second portions of the channel regions and connected to the common source line. These define an intermittent source line under the control gate layers. At the points of interruption, the second diffusion layers form selection transistors with the control gates, which are turned on or off depending on whether the corresponding cell is being read. When read, they prevent reading out any error data if the memory cell had been over-erased.