The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2001
Filed:
Nov. 30, 1998
Akira Sudo, Poughkeepsie, NY (US);
Kazumasa Sunouchi, Wappingers Falls, NY (US);
Akihiro Nitayama, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode formed on the storage node so as to bury the trench, the uppermost surface of a region of the storage node electrode contacting the diffusion region via the window being formed of a mono-crystalline silicon region. Thus, it is possible to improve the charge holding characteristic of a memory cell without deteriorating the performance of a cell transistor.