Semiconductor integrated circuit layout method

Abstract

In designing a layout for a deep-submicron semiconductor integrated circuit, a violational wire involving a violation of the delay limitation is extracted based on information representing a layout result obtained in a layout step. In order to extend a wire spacing between such an extracted wire and its neighboring wire to above a predetermined wire spacing, the neighboring wire is subjected to parallel displacement. If such a parallel displacement causes a distance of separation between the parallelly-displaced wire and its neighboring component to fall below a predetermined distance of separation, the component in question is shifted in order of extending the separation distance. Accordingly, even if the delay time of wire is dominant in comparison with that of element in regard to the signal propagation delay time, violations of the delay limitation occurring when the signal propagation delay time is less than a predetermined delay time can be canceled by a less number of steps.